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data sheet mos integrated circuit p p p p pd16666a 240-output lcd row driver 1997 document no. s12370ej2v0ds00 (2nd edition) date published october 1997 n printed in japan description the p pd16666a is a row (common) driver which contains a ram capable of full-dot lcd display. with 240 outputs, this driver can be combined with a column (segment) driver p pd16661a which contains a ram to display vga (640 by 480 dots), 1/2 vga, or 1/4 vga, etc. by combining it with the p pd16661a, the p pd16666a can provide four gray levels by frame rate control. with its built-in display ram in the column driver, the driver kit can reduce current consumption, thus making it most suitable for the display section of a pda or portable terminal. features ? lcd-driven voltage: 20 to 36 v ? duty: 1/240 ? driving type: 2 lines selected simultaneously ? output count: 240 outputs ? capable of gray level display: 4 gray levels (frame rate control) ordering information part no. package p pd16666an-xxx tcp (tab) p pd16666an-051 standard tcp (olb: 0.2 mm pitch; folding) the tcps external shape is custom-ordered. therefore, if you have a shape in mind, please contact an nec salesperson.
2 p p p p pd16666a block diagram liquid-crystal drive circuit selection control circuit bidirectional shift register level shifter x 1 to x 240 v dd v1 v ee dir v cc1 v ss l1 l2 doffb? stb frmb ? ? ? ? ? ? ? ? y ? ? ? ? ? ? ? ? t column driver interface q 1 to q 120 block function 1. liquid-crystal drive circuit this circuit selects and outputs the level for liquid-crystal driving. one of v dd , v ee , and v1 is selected by the output of the selection control circuit. 2. selection control circuit this circuit creates the signal which will select the level of the output signal, based on the output of the shift register circuit and the driving level power selection signals l1 and l2 3. bidirectional shift register circuit this refers to the 120-bit bidirectional shift register circuit. the dir signal can be used to switch over the shift direction. the data that has been entered from the frmb terminal is shifted by the row drive signal strobe (stb). 4. level shifter circuit this circuit transforms the 5-v signals to the high-voltage signals for liquid-crystal driving.
3 p p p p pd16666a pin functions classification pin name input/output pad no. function power v cc1 v ss v dd v ee v1 5 v power for level shifter gnd power for level shifter power for logic; liquid-crystal drive level power power for logic; liquid-crystal drive level power (gnd) liquid-crystal drive level power liquid-crystal display timing stb frmb doffb l1 l2 dir i i i i i i row drive strobe signal frame signal display off signal drive level power selection signal (1st line) drive level power selection signal (2nd line) shift direction selection signal: when l (dir = v ee ), x 1 o x 240 when h (dir = v dd ), x 240 o x 1 liquid-crystal drive output x 1 to x 240 o liquid-crystal drive output selects and outputs one of v dd , v ee , and v1. details of pin functions ? stb (input) refers to the input pin of the row drive strobe signal. the bidirectional shift register is shifted at stbs rising edge. ? frmb (input) refers to the input pin of the frame signal. the shift register data is read at stbs rising edge. ? dir (input) refers to the input pin of the drive outputs shift direction selection signal. when the shift direction selection signal (dir) is l, the shift data (selection signal) is shifted from the drive output x 1 to the x 240 direction. when h, it is shifted from the x 240 to the x 1 direction. ? doffb (input) refers to the input pin of the display off signal. it is placed in the display off status (all outputs at v1) at the l level. in the mean time, it reads the frame signal and returns to the normal display status at the h level. ? l1 & l2 (input) refer to the input pins of the drive level power selection signal. in the case of the liquid-crystal drive output, the two lines are selected simultaneously by the shift register. l1 selects the first line, and l2 the second line. both lines select v dd at h, and v ee at l.
4 p p p p pd16666a power supply sequence of chip set it is recommended to apply power in the following sequence. v cc2 o v cc1 o input o v dd , v ee o v0, v1, v2 be sure to apply lcd drive voltages v0, v1, and v2 last. v cc2 off on v dd note off on off on v ee note v0 off on v1 off on v2 off on v cc1 resetb input (a0-a16, csb, oeb, web, ubeb, d0-d15, doffb) off on 0 v 3.3 v 0 v 3.3 v 0.3 v cc2 4.5 v 0 s or more 0 s or more 100 ns or more 0 ns or more note v dd and v ee do not need to be turned on at the same time. caution turn off power to the chip set in the reverse sequence to the power application sequence.
5 p p p p pd16666a example of connecting internal schottky barrier diode of module to reinforce power supply protection (use a schottky barrier diode with vf = 0.5 v or less.) v dd v cc1 v2 v1 v0 v ss v ee connect the diodes enclosed in the dotted line when v 0 is not 0 v (gnd)
6 p p p p pd16666a electrical specifications absolute maximum ratings (t a = 25 q q q q c, v ss = 0 v) parameter symbol condition ratings unit supply voltage v cc1 C0.5 to +6.5 v v dd C v ee v cc1 d v dd , v ee d v ss 40 v1 v ee C 0.5 to v dd + 0.5 input voltage v i1 other than the dir pin C0.5 to v cc1 + 0.5 v i2 dir pin v ee C 0.5 to v dd + 0.5 output voltage v o v ee C 0.5 to +v dd + 0.5 operating temperature t a C20 to +70 q c storage temperature t stg C40 to +125 recommended operating range (t a = e e e e 20 to +70 q q q q c, v ss = 0 v) parameter symbol condition min. typ. max. unit supply voltage v cc1 4.75 5.25 v v dd C v ee v cc1 d v dd , v ee d v ss 20 36 v1 0 3 input voltage v i1 other than dir pin 0 v cc1 v i2 dir pin v ee v dd dc characteristics (unless otherwise specified, v cc1 = 4.75 to 5.25 v, v dd e e e e (v ee ) = 20 to 31 v, v cc1 d d d d v dd , v ee d d d d v ss , v1 = 0 to 3 v, v ss = 0 v, t a = e e e e 20 to 70 q q q q c) parameter symbol condition min. typ. max. unit high-level input voltage v ih1 other than the dir pin 0.8 v cc1 v v ih2 dir pin v dd e 0.3 (v dd Cv ee ) low-level input voltage v il1 other than the dir pin 0.2 v cc1 v il2 dir pin v ee +0.3 (v dd Cv ee ) driver on resistance r on load current = 100 p a 1.0 2.0 k : input leakage current i ih1 v in = v cc , other than the dir pin 1.0 p a i ih2 v in = v dd , dir pin 25 i il1 v in = 0 v, other than the dir pin C1.0 i il2 v in = v ee , dir pin C25 current consumption i cc1 frame frequency 70 hz at 200 320 p a i dd operation 120 210
7 p p p p pd16666a ac characteristics parameter symbol condition min. typ. max. unit stb high-level width t wsh 500 ns stb low-level width t wsl 500 frmb setup time t sf 100 frmb hold time t hf 100 stb rise time t r 150 stb fall time t f 150 output delay time t pdsx output no-load 300 t pdout 200
8 p p p p pd16666a ac characteristics waveform diagrams v cc1 v ss v cc1 v ss v ee v1 v dd v ss v cc1 v dd v1 v ee stb frmb doffb? xn xn + 2 0.9 v cc1 0.1 v cc1 0.5 v cc1 t wsh t wsl t sf 0.5 v cc1 0.5 v cc1 t pdsx t pdsx t pdsx t pdout v dd to v1 50 % v ee to v1 50 % t pdout v dd to v1 50 % v ee to v1 50 % t hf t r t f t pdsx
9 p p p p pd16666a level selection timing of liquid-crystal drive output the frmb is input in one frame twice. the stb is input into half a frame 121 times, and into one frame 242 times. dir v dd v ee frmb v cc1 v ss stb v cc1 v ss l1 v cc1 v ss l2 v cc1 v ss x1 v1 v dd v ee x2 x3 x4 x240 dir v dd v ee x240 v1 v dd v ee x239 x238 x237 x1 121 1 2 120 121 1 frame t1 t2 t3 t4 (when dir is h) 1 2 120 121 1 2 120 121 1 2 120 121 remark while the doffb is l, the x output remains at the v1 level. afterward, if it becomes h, the level of the x output is output timed with the above timing. note when the time lag between stb signal and the l1, l2 signals is large, hazard may occur in output.
10 p p p p pd16666a system configuration example an example of configuring a liquid-crystal panel of half-vga size (480 across by 320) by using four column drivers and two row drivers. ? each column driver sets the lsi no. with pl0, 1, and 2 pins. ? the dir pins of each column driver are all set to low level. ? only one of the column drivers is set to the master; all the others are set to the slave. signals are supplied from the master column driver to the slave column driver and to the row driver. ? connect an oscillator resistor to the osc1 and osc2 pins on the master, and leave these pins open on the slave. ? all the signals from the system (d0 to d15, a0 to a16, csb, oeb, web, ubeb, rdy, resetb, and doffb) are connected in parallel to the column driver. connect a pull-up resistor to the rdy signal. ? the test pin is used to test the lsi, and is open or grounded when the system is configured. y1 y160 y160 y1 y160 y1 y1 y160 240 240 stb frmb l1 l2 refrhb osc2 osc1 v cc2 master no. 0 slave no. 2 control csb, oeb web, ubeb scan direction scan direction slave no. 1 row driver row driver slave no. 3 rdy doffb resetb d0-d15 a0-a16 doutb/doffb?
11 p p p p pd16666a standard tcp package ( p p p p pd16666an-051) 17.70 17.40 a 27.10 27.30.3 17.70 18.00 18.00 26.00 25.00 4.00 17.81 12.50.3 12.20 2.50 3.50 0.30.3 4.750.03 1.9810.03 26.60 (1.50) (0.50) (1.90) 0.80 0.80 3.80 1.50 1.80 1.00 12.20 7.80 (13.70) 15.60 16.95 6.10 5.80 (56.20) 63.9490.08 27.10 27.30.3 0.70 0.70 1.50 1.50 7.3 +0 e4.3 japan d16666an-051 101 material base film adhesive copper foil plating solder resist : upilex-s : epoxy : electrolysis cu : sn : epoxy t = 75 s t = 12 m t = 25 s t = min. 0.25 m t = 25 m m m m m m this product is the flex specification figures in parenthesis denote a reference value corner radius unless otherwise specified r0.3 mm max. all tolerances unless otherwise specified 0.05 mm this figure is shown from the pattern side 5-pitch (23.75 mm) feed 2- 1.00 f p0.20 0.01 84 = 16.80 0.025 w0.10 0.15 p0.20 0.01 83 = 16.60 0.025 w0.10 0.015 p0.20 0.01 84 = 16.80 0.025 w0.10 0.15 22.4 e4.6 +0 a' coating area coating area flex resin coating area p0.80 0.01 18 = 14.40 0.025 w0.40 0.02
12 p p p p pd16666a 0.24 0.35 0.35 0.15 0.15 0.15 0.30 0.30 0.30 (1.90) 0.40 0.015 0.60 0.015 (13.70) 12.20 (1.50) 19.65 0.10 0.015 27.10 p0.20 detail of output side test pad and alignment mark ( 20) from pattern center from pattern center detail of alignment hole ( 20) r0.50 0.20 cu r0.80 cu r0.60 base hole 1.00 cu f 1.60 f cu 1.20 f base hole cu flex resin chip max. 0.9 a - a? sectional view tcp tape winding direction winding direction base film cu pattern is on the outside of the tape unwinding direction input leads output leads
13 p p p p pd16666a nc nc nc x240 x239 x238 x163 x162 x161 nc nc nc nc x160 x159 x158 x83 x82 x81 nc nc nc nc x80 x79 x78 x3 x2 x1 nc nc nc pd16666an -051 m nc vee v1 vdd vee dir stb l2 l1 doutb frmb vdd vcc1 vss vee vdd v1 vee nc
14 p p p p pd16666a [memo]
15 p p p p pd16666a [memo]
p p p p pd16666a no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5

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